1. Field of Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a dynamic random access memory (DRAM) and a method for manufacturing the same.
2. Description of the Related Art
Along with the modern microprocessors got surprised advance, its functions have become more marvelous and comprehensive. Accordingly, the modern microprocessors have a tremendous demanding on software to perform a more complex and more massive computation. To meet the demand, the memory process technology has become one of the most important semiconductor industry technologies.
In terms of the data storage type, a memory in general can be categorized into volatile memory (VM) and non-volatile memory (NVM). A DRAM belongs to a volatile memory (VM) and is formed by a plurality of memory cells. Each memory cell herein is formed by an active device and a capacitor, and all memory cells are coupled to one another by a word line (WL) and a bit line (BL).
On the other hand, DRAMs can be, in terms of the capacitor structure thereof, categorized into a DRAM with stacked capacitor and another DRAM with deep trench capacitor. For a DRAM having deep trench capacitor, the deep trench capacitor is formed in a substrate; therefore, in comparison with a DRAM with stacked capacitor, a planarizing process often can be exempt from the regular DRAM process, which allows fabricating a mini-sized memory. As the memory size gets smaller and smaller however, the DRAM having deep trench capacitor encounters numerous problems.
FIG. 1A is a schematic top view of a conventional deep trench DRAM. FIG. 1B is a schematic section view of a conventional deep trench DRAM, wherein the section view is made along sectioning plane A-A′ in FIG. 1A.
Referring to FIGS. 1 and 2, a DRAM includes a trench capacitor 102, a shallow trench isolation region (STI) 104, an active device 106 and a buried strap 108. The trench capacitor 102 is disposed in a substrate 100 and includes a lower electrode 110, a dielectric layer 112 and an upper electrode 114, wherein the upper electrode 114 is formed by a conductive layer 114a, a conductive layer 114b and a conductive layer 114c. A collar oxide layer 116 is disposed between the conductive layer 114b and the substrate 100. The shallow trench isolation region (STI) 104 is disposed in the substrate, and a part of shallow trench isolation region (STI) 104 is disposed in the trench capacitor 102. The active device 106 is deposed over the substrate 100, includes a source 118a/drain 118b and a gate structure 120. The active device 106 is coupled to the buried strap 108. The gate structure 120 includes a gate dielectric layer 120a, a gate 120b and a cap layer 120c. In addition, the source 118a is coupled to a bit line (BL) 126 through a plug 124. Spacers 122 are disposed at the sidewalls of the gate structure 120.
Since the active device 106 in the above-described DRAM is generally made by using a lithography etching process, the channel region length d of the active device is limited by the lithography etching process and can't be shortened further more so that the device integrity can't be advanced further more. On the other hand, while the channel region length d is shortened, the threshold voltage difference of the active device and so-called short channel effect are occurred. To resolve above-mentioned problem in the prior art, a solution was provided that the dopant density in the active device channel is increased, which however brings on a more unwanted field junction leakage current (FJL current) and degrades the device reliability.